1. Field of the Invention
This application relates to an apparatus for and method of testing semiconductor devices, and more particularly, to a method of increasing the number of semiconductors that can be tested at a time by improving the structure of a performance board of a testing apparatus and performing a parallel test on the doubled semiconductor devices.
2. Description of the Related Art
Semiconductor devices are produced in wafer forms and are assembled into a semiconductor package after an electrical die sorting (EDS) test. The semiconductor devices are finally tested electrically before being distributed to users. In particular, as the capacity of semiconductor memory devices and the number of semiconductor memory device pins increase rapidly, it becomes increasingly important to enhance efficiency of an electrical test process.
To enhance the efficiency of the electrical test, a tester for testing semiconductor memory devices has been developed, focusing on increasing speed and throughput, and shortening testing time of the tester. The testing time may be shortened using the following methods.
A first method is to change a testing method and modify a test program to shorten test time. A second method is to increase the number of semiconductor memory devices tested at a time, i.e., the number of devices under test (DUTs), in a parallel test.
FIG. 1 is a schematic perspective view of a conventional tester used to electrically test semiconductor devices. Referring to FIG. 1, a measuring unit needed to electrically test the semiconductor devices is included in a mainframe 22. The function of the mainframe 22 is extended to a test head 24 through a signal cable 20. A performance board 28 is mounted on top of the test head 24. The performance board 28 includes driver signal lines, I/O signal lines, power signal lines, and ground signal lines formed in a printed circuit pattern. Since a pogo pin block 19 is formed at the center of the performance board 28, the performance board 28 may be connected to a prober system or a handler and then used.
FIG. 2 is a sectional view of the test head 24 and the performance board 28 of FIG. 1. Referring to FIG. 2, the test head 24 includes a driver channel, an I/O channel, and a voltage supply unit (VSU) channel. The driver channel, the I/O channel, and the VSU channel are connected to a printed circuit patterns (not shown) of the performance board 28 by signal lines 30. The printed circuit patterns in the performance board 28 are connected to pogo pins 18.
In the EDS test, the pogo pins 18 are connected to a probe card of the prober system. In the final electrical test of a semiconductor package, a DUT board is connected into the pogo pins 18.
FIG. 3 illustrates signal lines connected from the test head 24 to a plurality of DUTs 40. Referring to FIG. 3, the test head 24 includes a driver signal line 10, an I/O signal line 12, and a power signal line 14 of a VSU. The driver signal line 10 is connected to address pins A0 through An of the DUTs 40 by a driver 11, via the performance board 28 and an interface board 32. The interface board 32 may be the probe card or the DUT board.
The I/O signal lines 12 are connected to data pins DQ0 through DQn of the DUTs 40 by the driver 11 and a comparator 13, via the performance board 28 and the interface board 32. The power signal lines 14 are connected to power pins VDD of the DUTs 40 by the driver 11, via a relay 16 of the performance board 28 and the interface board 32.
If it is determined that a DUT is defective as a result of a parallel electrical test, the relay 16 is turned off, thereby preventing DUTs adjacent to the defective DUT or the interface board 32, such as the probe card, from being damaged.
FIG. 4 is a block diagram for illustrating a connection state of the power signal line 14 in the performance board 28. Referring to FIG. 4, in the parallel test, the power signal line 14 in the printed circuit pattern of the performance board 28 is connected to the power pin VDD of each of the DUTs 40. In the parallel electrical test, all of first through nth relays 16-1 through 16-n are connected. However, if a second DUT is found defective in the parallel test, the second relay 16-2 is turned off, thereby preventing DUTs adjacent to the second DUT from being damaged or a needle of the interface board 32 of FIG. 3 from melting.
However, the method described above is a mechanism for testing a predetermined number of DUTs in a parallel electrical test process. To increase the number of DUTs, a new control method in terms of software and hardware is required.